Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Economics of design and test for electronic circuits and systems
Economics of design and test for electronic circuits and systems
ASIC Yield Estimation at Early Design Cycle
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference
Test generation costs analysis and projections
DAC '80 Proceedings of the 17th Design Automation Conference
Application of Deterministic Logic BIST on Industrial Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Framework to evaluate Test Tradeoffs in Embedded Core Based Systems-Case Study on TT's TMS320C27xx
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Logic BIST for Large Industrial Designs: Real Issues and Case Studies
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
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This paper presents a general economic modelingmethodology for digital semiconductor production testapproaches. The methodology can be used to quantifytrade-offs and evaluate test approaches, includingdistributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural trade-offs,with modeled cost contributions that include testtime, die area, yield, time-to-market, and engineeringeffort. It allows one to forecast how those test approachesscale with technology progress. The economic models aremodular and expandable. The modeling methodology willbe illustrated on various test approaches.