Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test

Authors:
Andrew C. Evans
Affiliations:
-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

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Abstract

This paper develops a Semiconductor TestEconomic Model that can easily be applied to loweringoverall cost of test and improving throughput. The"Model", designed to take the complexity out of TestEconomics, describes all the variables that make up CostPer Unit (CPU), and using managerial economicconcepts, illustrates how they interact with each other,as well as the overall production goal of minimizingcosts while maximizing throughput. This paper is writtenfor Test Managers, Test Engineers, Product Engineers,and ATE Capital Equipment Buyers for the purpose ofgaining insight analyzing test economics, in order tomake better decisions on everyday Manufacturing issuesrelated to: test time reduction, multisite testing, yield,handler index time, ATE Utilization, and ATEpurchasing.