Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A new methodology for improved tester utilization
Proceedings of the IEEE International Test Conference 2001
Tackling test trade-offs from design, manufacturing to market using economic modeling
Proceedings of the IEEE International Test Conference 2001
Enhanced reduced pin-count test for full-scan design
Proceedings of the IEEE International Test Conference 2001
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Set of Benchmarks fo Modular Testing of SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Test Economics for Multi-site Test with Modern Cost Reduction Techniques
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Applications of Semiconductor Test Economics, and Multisite Testing to Lower Cost of Test
ITC '99 Proceedings of the 1999 IEEE International Test Conference
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test Infrastructure Design for the Nexperia" Home Platform PNX8550 System Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
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Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow to test multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT, in order to maximize the test throughput for a given SOC and ATE. The on-chip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC Test Benchmarks.