On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
IEEE Transactions on Computers
Multiple-constraint driven system-on-chip test time optimization
Journal of Electronic Testing: Theory and Applications
A test pattern ordering algorithm for diagnosis with truncated fail data
Proceedings of the 43rd annual Design Automation Conference
Modular and rapid testing of SOCs with unwrapped logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Substrate Testing on a Multi-Site/Multi-Probe ATE
Journal of Electronic Testing: Theory and Applications
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
A diagnosis algorithm for extreme space compaction
Proceedings of the Conference on Design, Automation and Test in Europe
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We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In Step 1, an efficient technique based on enhanced rectangle packing is used to design the wrapper/TAM architecture such that the SOC test suite fits in a single ATE memory load. Furthermore, the total TAM width for the SOC is minimized, thereby reducing routing complexity and hardware cost. Minimum TAM width directly leads to the minimization of the number of ATE channels used, thus enabling multi-site testing. In Step 2, test scheduling is performed such that "idle" bits appearing between core tests on ATE channels are moved to the end of each channel. This reduces the memory depth allocated to the channels from the pool of ATE memory. The saved memory can be mapped to the remaining ATE channels to test other SOCs, thereby further facilitating multi-site testing. We present experimental results on our technique for five benchmark SOCs.