Components quality/reliability handbook
Components quality/reliability handbook
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Test Length in a Self-Testing Environment
IEEE Design & Test
Built-In Self-Test Trends in Motorola Microprocessors
IEEE Design & Test
Exploiting Defect Clustering to Screen Bare Die for Infant Mortality Failures: An Experimental Study
ITC '99 Proceedings of the 1999 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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How thorough must functional testing of digital ICs be to guarantee adequate quality? In other words, is fault grading necessary? If yes, how high must the single-stuck fault coverage be? This paper shows that, not only is fault grading required, but that extremely high single-stuck fault coverage is probably necessary. The results presented here are extensions of previous work in this area by T.W. Williams. The extensions consist of: 1. removing the assumption of a one-to-one correspondance between chip defects and single-stuck faults, 2. demonstrating that, for high quality levels, the dependence of quality on test coverage is linear rather than exponential; and that for high yields, the dependence of quality on yield is also linear; and 3. showing that the yield used in the calculations should be functional rather than die yield. The theoretical results are compared with data obtained from measurements at a production IC facility.