Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 44th annual Design Automation Conference
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
3D-Stacked Memory Architectures for Multi-core Processors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Parametric yield management for 3D ICs: Models and strategies for improvement
ACM Journal on Emerging Technologies in Computing Systems (JETC)
3-D Content Addressable Memory Architectures
MTDT '09 Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Maximizing the functional yield of wafer-to-wafer 3-D integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Is 3D integration an opportunity or just a hype?
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of a 3-D fully depleted SOI computational RAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Yield enhancement for 3D-stacked memory by redundancy sharing across dies
Proceedings of the International Conference on Computer-Aided Design
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Proceedings of the International Conference on Computer-Aided Design
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A three-dimensional (3D) integrated circuit (IC) with multiple dies vertically connected by through-silicon-via (TSV) offers many benefits over current 2D ICs. Multicore logic-memory die stacking has been considered as one candidate for 3D ICs by utilizing the TSV to provide high data bandwidth between logic and memory. However, 3D ICs suffer from the low-yield issue. This article proposes effective yield-enhancement techniques for multicore die-stacked 3D ICs. Two reconfiguration schemes are proposed to logically swap the positions of cores in the dies of 3D ICs such that the yield of 3D ICs is increased. Two algorithms also are proposed to determine the reconfiguration effectively. Simulation results show that the proposed reconfiguration schemes can achieve a yield gain ranging from 1% to 11%.