Design of a 3-D fully depleted SOI computational RAM

Authors:
John C. Koob;Daniel A. Leder;Raymond J. Sung;Tyler L. Brandon;Duncan G. Elliott;Bruce F. Cockburn;Lisa McIlrath
Affiliations:
Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada;resides in Edmonton, AB, Canada;Broadcom Corporation, Santa Clara, CA;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada;R3Logic Inc., Cambridge, MA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

We introduce a three-dimensional (3-D) processor-in-memory integrated circuit design that provides progressively increasing processing power as the number of stacked dies increases, while incurring no extra design effort or mask sets. Innovative techniques for processor/memory redundancy and fast global bus evaluation are described. The architecture can be augmented with a nearest-neighbor physical 3-D communications network that can substantially reduce interconnect lengths and relieve routing congestion. The test chip, with 128 Kb of memory and 512 processing elements (PEs) on two fully depleted silicon-on-insulator (SOI) dies, can achieve a peak of 170 billion-bit-operations per second at 400 MHz.