A 3-D cache with ultra-wide data bus for 3-D processor-memory integration

Authors:
Aamir Zia;Philip Jacob;Jin-Woo Kim;Michael Chu;Russell P. Kraft;John F. McDonald
Affiliations:
Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY;Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY;Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY;Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY;Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY;Electrical, Computer and Systems Engineering, Department and the Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

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Abstract

Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth and low latency on-chip cache. This paper presents a three-tier, 3-D 192-kB cache for a 3-D processor-memory stack. The chip is designed and fabricated in a 0.18 µm fully depleted SOI CMOS process. An ultra wide data bus for connecting the 3-D cache with the microprocessor is implemented using dense vertical vias between the stacked wafers. The fabricated cache operates at 500 MHz and achieves up to 96 GB/s aggregate bandwidth at the output.