Design of a 3-D fully depleted SOI computational RAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Abstract: We describe the design of an embedded 128-Kb Silicon-On-Insulator (SOI) CMOS SRAM, which is integrated alongside an array of pitch-matched processing elements to provide massively-parallel data processing within one integrated circuit. An experimental 0.25-_mfully-depleted SOI process was used. The design and layout of the SOI memory core and results from calibrated circuit simulations are presented. The impact of the floating body effect is investigated for both memory reads and writes. We describe threshold mismatch effects in the sense amplifier that result from the floating body voltage. Floating body effects are compared against simulated results for an SRAM designed in a 0.25-µm partially-depleted SOI process.