Design of a 3-D fully depleted SOI computational RAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Computational RAM (C 驴RAM) is a logic-enhanced memory architecture that has already shown promise in several demanding applications. A C 驴RAM chip integrates a conventional memory array along with a linear array of bit-serial processing elements (PEs). The narrow PEs are pitch-matched to the columns of the memory array to access the high internal memory bandwidth and to produce an efficient layout. After a memory row has been accessed, the PEs can perform many thousands of bit-serial operations in parallel on the fetched bits as well as values stored locally in PE registers. We consider the problem of efficiently testing C 驴RAMs for functional faults in the PEs and the memory array. It is shown that the linear array of PEs is a powerful resource that can be used to generate standard memory test patterns. The test time for the PEs plus their local memories is much less than the test time of the memories alone.