Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Three-dimensional (3-D) integration is an emerging integrated circuit technology. Semiconductor memory is very suitable to be realized using 3-D technology due to its regularity. Different from random access memories (RAMs), a content addressable memory (CAM) has a priority address encoder (PAE) for evaluating the comparison result. The existing of PAE causes that the design of 3-D architectures for CAMs is more difficult than that for RAMs. This paper proposes a matchlinepartitioned 3-D architecture and a searchline-partitioned 3-D architectures for CAMs. An inter-layer interleaving scheme is proposed to distribute PAE logic circuits evenly in two layers such that the footprint of a 3-D CAM is minimized. Experimental results show that the proposed 3-D CAM have better search performance for most of CAMs used in the industry.