DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
IEEE Transactions on Computers
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Detecting bridging faults with stuck-at test sets
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Proceedings of the conference on Design, automation and test in Europe
Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
On test data compression and n-detection test sets
Proceedings of the 40th annual Design Automation Conference
Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Comparing Functional and Structural Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Balanced Excitation and Its Effect on the Fortuitous Detection of Dynamic Defects
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
Worst-Case and Average-Case Analysis of n-Detection Test Sets
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
N-detection under transparent-scan
Proceedings of the 42nd annual Design Automation Conference
On N-Detect Pattern Set Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Generation of broadside transition fault test sets that detect four-way bridging faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Test vector chains for increased targeted and untargeted fault coverage
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Resistive bridging fault simulation of industrial circuits
Proceedings of the conference on Design, automation and test in Europe
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.