The influences of fault type and topology on fault model performance and the implications to test and testable design

Authors:
Kenneth M. Butler;M. Ray Mercer
Affiliations:
Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX;Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 4
Cited 4

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers
Test pattern generation for sequential MOS circuits by symbolic fault simulation

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
CATAPULT: concurrent automatic testing allowing parallelization and using limited topology

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Test Routines Based on Symbolic Logical Statements

Journal of the ACM (JACM)

A branching process model for observability analysis of combinational circuits

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Defect-Oriented Testing and Defective-Part-Level Prediction

IEEE Design & Test
Enhanced testing performance via unbiased test sets

EDTC '95 Proceedings of the 1995 European conference on Design and Test
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Quantified Score

Hi-index	0.00

Visualization

Abstract

A new method, Difference Propagation, is proposed to analyze fault models in combinational circuits. It propagates Boolean functional information represented by ordered binary decision diagrams. Results are presented concerning exact detectabilities and syndromes for a set of benchmark circuits. The data suggest answers to open questions in CAD and represent the first data of this type for bridging faults. The information is shown to affect testable design as well as test generation.