Proceedings of the conference on Design, automation and test in Europe
Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in addition to more site observations) balanced excitation is essential for detection of these defects, and we present ametric for estimating this degree of balance. We also show that excitation balance correlates with the parameter 驴 in the MPG-D defective part level model.