Modelling extremal events: for insurance and finance
Modelling extremal events: for insurance and finance
Practical Oscillation-Based Test of Integrated Filters
IEEE Design & Test
Test Metrics for Analog Parametric Faults
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Production Testing of Rf and System-On-A-Chip Devices for Wireless Communications (Artech House Microwave Library)
Defect Level as a Function of Fault Coverage
IEEE Transactions on Computers
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing
Journal of Electronic Testing: Theory and Applications
Evaluation of analog/RF test measurements at the design stage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect level evaluation in an IC design environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Nonlinear decision boundaries for testing analog circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
The high cost of analog circuit testing has sparked off intensified efforts to identify robust and low-cost alternative tests that could effectively replace the standard specification-based tests. Nevertheless, the current practice is still specification-based testing. One of the primary reasons is the lack of tools to evaluate in advance the indirect costs (e.g. parametric test escape and yield loss) associated with alternative tests. To this end, in this paper, we present a method to estimate test escape and yield loss that occur as a result of replacing one costly specification test by one low-cost alternative test. This evaluation is performed at the design or test development stage with parts per million (PPM) accuracy. The method is based on extreme value theory and on a fast simulation technique of extreme events called statistical blockade.