On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design*This work is conducted as part of activities of the physical design methodology study group, EDA technical committee of JEITA.

Authors:
Takashi Sato;Junji Ichimiya;Nobuto Ono;Koutaro Hachiya;Masanori Hashimoto
Affiliations:
The author is with Renesas Technology Corporation, Kodaira-shi, 187-8588 Japan. E-mail: takashi@ieee.org,;The author is with Ricoh Corporation, Ikeda-shi, 563-8501 Japan.,;The author is with JEDAT Incorporated, Kitakyushu-shi, 808-0135 Japan.,;The author is with NEC Electronics Corporation, Kawasaki-shi, 211-8668 Japan.,;The author is with the Graduate School of Information Science and Technology, Osaka University, Suita-shi, 565-0871 Japan.,
Venue:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Year:
2005

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Abstract

This paper quantitatively analyzes thermal gradient of SoC and proposes a thermal flattening procedure. First, the impact of dominant parameters, such as area occupancy of memory/logic block, power density, and floorplan on thermal gradient are studied quantitatively. Temperature difference is also evaluated from timing and reliability standpoints. Important results obtained here are 1) the maximum temperature difference increases with higher memory area occupancy and 2) the difference is very floorplan sensitive. Then, we propose a procedure to amend thermal gradient. A slight floorplan modification using the proposed procedure improves on-chip thermal gradient significantly.