A heuristic algorithm for the fanout problem
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs
Proceedings of the 1997 international symposium on Physical design
Greedy wire-sizing is linear time
ISPD '98 Proceedings of the 1998 international symposium on Physical design
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Fanout optimization under a submicron transistor-level delay model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On the global fanout optimization problem
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Meeting delay constraints in DSM by minimal repeater insertion
DATE '00 Proceedings of the conference on Design, automation and test in Europe
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We present a novel algorithm for delay-constrained optimization of combinational logic, extending the state-of-the-art sizing algorithm [1] based on Lagrangian relaxation. We tightly integrate fanout tree construction, buffer insertion/sizing and gate sizing; thereby achieving more optimization than if, they were performed independently. We consider the network in its entirety, thereby taking full advantage of the slacks available on the non-critical paths. We have implemented our algorithm and experimented with it on ISCAS-89 benchmark circuits; the results demonstrate that it is effective as well as fast.