Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs

Authors:
Juho Kim;Cyrus Bamji;Yanbin Jiang;Sachin Sapatnekar
Affiliations:
Sogang University;Cadence Design Systems;Iowa State University;Iowa State University
Venue:
Proceedings of the 1997 international symposium on Physical design
Year:
1997

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Abstract