Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On Finding the Maxima of a Set of Vectors
Journal of the ACM (JACM)
Delay budgeting for a timing-closure-driven design method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Efficient Data Structure for Maxplus Merge in Dynamic Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The traditional repeater insertion in an integrated circuit (IC) is aimed at eliminating cycle (setup) time violations at the worst process corner. Subsequently, special measures are adopted to remedy hold-time violations identified at the best process corner. However, aggressive delay reduction for fixing setup time violations could introduce new hold-time violations that did not exist before. Designers are usually un-ware of these newly created hold-time violations as they do not compare hold-time violations pre and post repeater insertion. However, identifying these nets and rerunning them with the presented technique to deal with hold time requirements can reduce the number of repeaters and design turn-around time. The power vs. delay trade-off technique presented is found to be extremely useful in limiting the number of repeaters to an acceptable limit. Concurrent treatment of setup time and hold time helps in better timing convergence for the affected nets by avoiding creation of new violations. Satisfying a minimum and a maximum slews along with accurate RC and gate timing models helps attain good timing correlation/convergence with a static timer.