Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Performance-oriented technology mapping
Performance-oriented technology mapping
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power optimal dual-Vdd buffered tree considering buffer stations and blockages
Proceedings of the 42nd annual Design Automation Conference
Fast dual-vdd buffering based on interconnect prediction and sampling
Proceedings of the 2007 international workshop on System level interconnect prediction
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Proceedings of the 2008 international symposium on Physical design
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Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful approaches to improve circuit speed and correct timing violations after global placement. This paper presents a dynamic- programming based algorithm for performing net topology construction and buffer insertion and sizing simultaneously under the given buffer-placement blockages. The differences from some previous works are that (1) the buffer locations are not pre-determined, (2) the multi-pin nets are easily handled, and (3) a line-search routing algorithm is implemented to speed up the process. Heuristics are used to reduce the problem complexity, which include limiting number of intermediate solutions, using a continuous buffer sizing model, and restricting the buffer locations along the Hanan graph. The resulting algorithm, named BRBP, was applied to a number of industrial designs and achieved an average of 7.9% delay improvement compared to a conventional design.