VIPER: an efficient vigorously sensitizable path extractor
DAC '93 Proceedings of the 30th international Design Automation Conference
The kernel, the bargaining set and the reduced game
International Journal of Game Theory
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Hierarchical functional timing analysis
DAC '98 Proceedings of the 35th annual Design Automation Conference
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers
Timing analysis speed-up using a hierarchical and a multimode approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Timing analysis of complex state-of-the-art designs demands efficient algorithms able to cope with design complexity. Exploring the hierarchical information generally encountered in complex designs became mandatory to perform functional timing analysis (FTA) in acceptable execution times. Although several hierarchical FTA approaches exist, only path-based hierarchical FTA is able to identify global critical paths, thus helping designers in the optimization task. In this paper we propose two versions of path-based hierarchical FTA strategies. These versions are compared to flat-mode FTA and to commercial FTA tools that operate in hierarchical mode.