Considering zero-arrival time and block-arrival time in hierarchical functional timing analysis

  • Authors:
  • Daniel Lima Ferrão;Ricardo Reis;José Luís Güntzel

  • Affiliations:
  • UFRGS, Universidade Federal do Rio Grande do Sul, Instituto de Informática, Porto Alegre, Brazil;UFRGS, Universidade Federal do Rio Grande do Sul, Instituto de Informática, Porto Alegre, Brazil;UFPel, Universidade Federal de Pelotas, Departamento de Informática, Pelotas, Brazil

  • Venue:
  • PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
  • Year:
  • 2006

Quantified Score

Hi-index 0.00

Visualization

Abstract

Timing analysis of complex state-of-the-art designs demands efficient algorithms able to cope with design complexity. Exploring the hierarchical information generally encountered in complex designs became mandatory to perform functional timing analysis (FTA) in acceptable execution times. Although several hierarchical FTA approaches exist, only path-based hierarchical FTA is able to identify global critical paths, thus helping designers in the optimization task. In this paper we propose two versions of path-based hierarchical FTA strategies. These versions are compared to flat-mode FTA and to commercial FTA tools that operate in hierarchical mode.