A hierarchical approach towards system level static timing verification of SoCs

Authors:
Rupsa Chakraborty;Dipanwita Roy Chowdhury
Affiliations:
Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, INDIA;Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, INDIA
Venue:
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Year:
2009

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Abstract

The high complexity and the core diversities make timing verification of an entire flattened SoC design a tedious process. In this paper, at first the various timing issues related to modular SoC verification have been investigated and then a bottom-up hierarchical approach of verifying the system level timing of an SoC, is presented. The timing abstractions of the cores are assumed to be provided by the core vendors. The interconnection delays of the SoC may be extracted from the SDF file generated after post layout simulation. The hierarchical approach provides a fast and systematic way of timing verification, as opposed to the flattened approach. Experiments were conducted on synthetic SoCs, using ISCAS benchmark circuits as cores. Results validate the claim of the proposed approach.