Provably correct critical paths
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Certified timing verification and the transition delay of a logic circuit
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Valid clocking in wavepipelined circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Circuit complexity: from the worst case to the average case
STOC '94 Proceedings of the twenty-sixth annual ACM symposium on Theory of computing
Exact minimum cycle times for finite state machines
DAC '94 Proceedings of the 31st annual Design Automation Conference
Gate-level timing verification using waveform narrowing
EURO-DAC '94 Proceedings of the conference on European design automation
Path sensitization of combinational circuits and its impact on clocking of sequential systems
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Hierarchical timing analysis using conditional delays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Event propagation conditions in circuit delay computation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Propagation of last-transition-time constraints in gate-level timing analysis
Proceedings of the conference on Design, automation and test in Europe
Event propagation for accurate circuit delay calculation using SAT
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SAT based timing analysis for fixed and rise/fall gate delay models
Integration, the VLSI Journal
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