Timing analysis with known false sub graphs
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Removing user specified false paths from timing graphs
Proceedings of the 37th Annual Design Automation Conference
Combinatorial Algorithms
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
Efficient static timing analysis and applications using edge masks
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Improving the efficiency of static timing analysis with false paths
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent false paths and multi-cycle paths. The complexity of the subgraph representation is reduced to improve efficiency. Finally, we present theorems to show that the unified framework produces correct timings. The experimental results demonstrate that the minimization is effective for both artificial and industry test cases.