Hierarchical timing verification system
Computer-Aided Design
Hierarchical design verification for large digital systems
DAC '81 Proceedings of the 18th Design Automation Conference
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
On the general false path problem in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A novel approach to accurate timing verification using RTL descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Efficient algorithms for extracting the K most critical paths in timing analysis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A polynomial-time heuristic approach to approximate a solution to the false path problem
DAC '93 Proceedings of the 30th international Design Automation Conference
A case against event-driven simulation for digital system design
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Static timing analysis including power supply noise effect on propagation delay in VLSI circuits
Proceedings of the 38th annual Design Automation Conference
A new algorithm for transistor sizing in CMOS circuits
EURO-DAC '90 Proceedings of the conference on European design automation
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Due to the rapid progress in semiconductor technology, the number of gates that can be placed in a chip increases dramatically. Existing algorithms for timing analysis have difficulties when dealing with large designs. A new algorithm for timing analysis is proposed in this paper. This algorithm enumerates all the paths with delay greater than a given threshold. The execution time of the proposed algorithm is proportional to the number of paths generated. Therefore, it is suitable for large designs.Classification: timing verification.