SIMMOS: a multiple-delay switch-level simulator

Authors:
Dan Adler
Affiliations:
Motorola Semiconductor Israel (MSIL), 147 Bialik St., Ramat-Gan 61047, Israel
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

Citing 5
Cited 0

Performance evaluation of FMOSSIM, a concurrent switch-level fault simulator

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
A transistor-level logic-with-timing simulator for MOS circuits

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Timing analysis for nMOS VLSI

DAC '83 Proceedings of the 20th Design Automation Conference
STAFAN: An alternative to fault simulation

DAC '84 Proceedings of the 21st Design Automation Conference
Switch-level delay models for digital MOS VLSI

DAC '84 Proceedings of the 21st Design Automation Conference

Quantified Score

Hi-index	0.01

Visualization

Abstract

SIMMOS is a multiple-delay logic simulator for MOS VLSI circuits based on the switch-level model. In addition to finding the ternary logic state at each node, SIMMOS estimates the time delay required for that state to become valid. The delay calculation method, based on the theory of RC trees, is introduced as a natural extension of the dominant-path algorithm used for node state evaluation.Multi-level simulation in SIMMOS is achieved by using special models for gate-level primitives, and the ability to drive, and be driven by an RTL simulation environment.For test-pattern grading, SIMMOS uses a probabilistic fault analysis algorithm, modified to operate on bidirectional as well as gate-level models.