Switch level random pattern testability analysis

Authors:
Mehmet A. Cirit
Affiliations:
Silicon Compiler Systems, Martinville Rd, P.O. Box 16, Liberty Corner, New Jersey
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

Citing 3
Cited 1

PROTEST: a tool for probabilistic testability analysis

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Timing analysis for nMOS VLSI

DAC '83 Proceedings of the 20th Design Automation Conference
STAFAN: An alternative to fault simulation

DAC '84 Proceedings of the 21st Design Automation Conference

An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSI

EDTC '96 Proceedings of the 1996 European conference on Design and Test

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present a new statistical, probabilistic algorithm for calculating controllability and observability for signal nets assuming the circuit can be described as a directed graph of unidirectional MOS switches. Application of the new algorithms to the testability analysis of CMOS circuits is described.