Introduction to VLSI Systems
Path delay analysis for hierarchical building block layout system
DAC '83 Proceedings of the 20th Design Automation Conference
Bounds on the saved area ratio due to PLA folding
DAC '83 Proceedings of the 20th Design Automation Conference
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The analog behavior of digital VLSI circuits is investigated. A theory based on nonlinear Thevenin equivalent circuits and RC ladder networks is developed. We obtain closed form expressions for the upper and lower bounds on propagation delay through a string of inverters. We generalize this to multiple-input, multiple-output gates and show that the problem of estimating signal propagation delays in VLSI circuits may be reduced to the problem of summing the step responses of a set of linear RC networks. As well as having implications for a computationally efficient timing simulator, the theory begins the formalization of the fundamental properties of digital integrated circuits.