Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
IEEE Transactions on Computers
Combinational static CMOS networks
Proc. of the Aegean workshop on computing on VLSI algorithms and architectures
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
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Switching theory has existed for many years as a well established discipline which has been useful to both the circuit designer and the general planner. It survived intact from the early days of relay and vacuum tube circuits to later transistor technology. But the development of CMOS circuits in recent years and their increased use in most switching applications have made it clear that classical switching theory is not sufficient. The new technology has been with us long enough so that an extension of switching that deals specifically with CMOS circuits is in order.A few excellent papers have appeared which have dealt in a theoretical way with the design of CMOS circuits, for example see Brzozowski - Yoeli [1], and also Bryant [2] and Ramachandran [3], but many aspects of the subject remain to be investigated.In [1] a switch level model for CMOS circuits was described which supercedes the Boolean switch level model and takes account of the special properties of MOS transistors in the design of a combinational cell.In the present paper we approach some other aspects of CMOS circuit design which require special treatment. Specifically, a combinational cell may often be designed so as to produce an enhanced Boolean function which includes a “memory” state u as well as the usual 0 and 1. This memory state is a result of the ability of a node to store charge if it is not being driven in one direction or the other.We wish to study the way the inclusion of such memory states affects the way designs are carried out and to see what limitations still exist in the types of circuits that can be realized.As with the other authors, we recognize the advantage of dealing with combinational or feedback-free circuits. These advantages include ease of analysis, not having to worry about oscillation, direct calculations of time delay, and ultimately perhaps the development of algebraic methods of design.To fix our model we shall assume that our basic cells are of the “separated” type shown in Figure 1. The inputs to the cell are all applied to the gates of the transistors. A network of p-channel transistors representing a monotone Boolean function ƒ connects the output z to the positive terminal of the voltage supply (called 1) and a network of n-channel transistors representing a monotone Boolean function g connects the output z to the negative terminal (called 0). Further, we shall assume that the Boolean functions ƒ and g bear the relationship fd ⊇ g to each other (or equivalently gd ⊇ ƒ) where fd represents the dual of ƒ and similarly for g.The case in which fd = g corresponds to the case in which the cell is strictly Boolean (i.e. it exhibits no memory) and the output z has the value g. In general, however, there may be some input configurations for which fd = 1 and g = 0. For these inputs we assign z the value u meaning that the output is not being driven and will retain whatever value it had previously. A model for this type of cell can be imagined using ordinary Boolean elements and a special memory element called the @@@@-element (or inverse of the C-element). It has the table shown below in Figure 2 in which if the two inputs agree the output is their inverse while if they disagree the output retains its previous value.Although seemingly specialized, our network model is no less powerful than those previously considered for feedback-free circuits in terms of functions that can be realized. Indeed, in the separated model shown in Figure 1, we may think of the cell as representing a mapping z : {0, 1}n → {0, u, 1}, where n is the number of Boolean inputs. If the complements of the inputs are not available then the function must be nonincreasing if we assume the formal ordering 0 u z : {0, 1}n → {0, u, 1} it is possible to design networks ƒ and g which realize z as a separated cell. The choice of the Boolean functions ƒ and g is unique in this case.If complements of the inputs are available then the restriction that z be nonincreasing may be removed. However, in this case special precautions must be taken to avoid transient effects.An acyclic charge-storage circuit is a cascade connection of such basic cells, where inputs to a given stage may only be taken either from the primary inputs or from the outputs of previous stages.Even though such a cascade does not contain feedback it must be thought of as an asynchronous sequential circuit because of the presence of memory states which may occur at the nodes. However, it is a very special type of sequential machine as is shown by Theorem 1 below.Let M = Q, &dgr; Q is the internal state set, and &dgr; : Q x &Sgr; → Q is the transition function which gives the next state when the present state and input configuration are known. We write &dgr;a : Q → Q for the restriction of &dgr; to a &egr; &Sgr;. Then the set {&dgr;a | a &egr; &Sgr;} represents a set of mappings from Q into Q.