Design rule verification based on one dimensional scans
DAC '78 Proceedings of the 15th Design Automation Conference
F/LOGIC - An interactive fault and logic simulator for digital circuits
DAC '76 Proceedings of the 13th Design Automation Conference
A Design Verification and Logic Validation System
DAC '77 Proceedings of the 14th Design Automation Conference
Digital logic simulation at the gate and functional level
DAC '79 Proceedings of the 16th Design Automation Conference
A functional level modelling language for digital simulation
DAC '82 Proceedings of the 19th Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
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A set of programs used in the design of custom hand packed and standard cell MOS circuits is described. The programs cover logic simulation, filter analysis, circuit simulation, timing simulation, circuit extraction from layout, design tolerance checking, connectivity checking and user interface facilities. A cell documentation system is used to tie together the various design support packages.