Introduction to VLSI Systems
Logic design automation of MOS combinational networks with fan-in, fan-out constraints
DAC '78 Proceedings of the 15th Design Automation Conference
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Operational features of an MOS timing simulator
DAC '75 Proceedings of the 12th Design Automation Conference
Logic design automation of diagnosable MOS combinational logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
Aquarius: Logic simulation on an Engineering Workstation
DAC '83 Proceedings of the 20th Design Automation Conference
Simulating pass transistor circuits using logic simulation machines
DAC '83 Proceedings of the 20th Design Automation Conference
An MOS digital network model on a modified thevenin equivalent for logic simulation
DAC '84 Proceedings of the 21st Design Automation Conference
Transmission gate modeling in an existing three-value simulator
DAC '82 Proceedings of the 19th Design Automation Conference
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
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Modelling strategies and techniques are given for static and dynamic MOS transistors in a 4-state (0/low, 1/high, Z/high-impedance, U/undefined) logic simulator environment. General MOS modelling problems are presented and a set of workable solutions are developed. Experience with these techniques is shown along with examples of NMOS simulation applications. This paper discusses a technique with specific conventions for modelling MOS devices at the “logical transistor” gate level. The technique is not the optimal general solution, but was found to be satisfactory for retrofitting an existing 4-state logic simulator to include MOS capabilities. The technique is not meant to replace analog circuit simulation, but is aimed at increasing the accuracy of MOS logic (gate level) simulations. We begin with a general bus model and extend it to handle transistors, pullups and pulldowns, and dynamic MOS transfer gates. Extensions are shown for a bidirectional transfer gate model that can be connected in any topological configuration.