Exclusive simulation of activity in digital networks
Communications of the ACM
BIMOS, an MOS oriented multi-level logic simulator
DAC '83 Proceedings of the 20th Design Automation Conference
A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge
DAC '81 Proceedings of the 18th Design Automation Conference
The concurrent simulation of nearly identical digital networks
DAC '73 Proceedings of the 10th Design Automation Workshop
A multiple delay simulator for MOS LSI circuits
DAC '80 Proceedings of the 17th Design Automation Conference
Switch-level concurrent fault simulation based on a general purpose list traversal mechanism
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A novel analytical model of MOS digital networks, which is based on a modified Thevenin equivalent, is described. The model can handle all the primary circuits inherent in MOS technology, such as transistor logics, wired-ORs, tri-state circuits, charge-share operation, and bidirectional pass transistors etc., with precise estimation of delay time. The model has been implemented in a logic/fault simulator, named HASL-GT. Performance of 4 to 10 k events/sec has been obtained on HITAC M-200H(8MIPS). Fault simulation capability has also been implemented using the concurrent method.