Switch level hot-carrier reliability enhancement of VLSI circuits

Authors:
A. Dasgupta;R. Karri
Affiliations:
-;-
Venue:
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Year:
1995

Citing 8
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Abstract

Long-term reliability of MOS VLSI circuits is becoming an important issue with rapid advances in VLSI technology and increasing VLSI chip densities. Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying MOSFETs in the circuit that are most susceptible to hot-carrier effects. Subsequently, we outline two techniques-(i) reordering of inputs to logic gates and (ii) selective MOSFET siting-to reduce the hot-carrier susceptibility of these critical MOSFETs. Finally, we show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption. The algorithms are incorporated into SIS and are evaluated on the ISCAS-MCNC91 benchmark suite.