Communications of the ACM - Special section on computer architecture
ACM Transactions on Programming Languages and Systems (TOPLAS)
Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
The C++ programming language
Behavioral models take the pain out of system simulation
Computer Design
Architecture and design of the MARS hardware accelerator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A Preemptive Scheduling Mechanism for Accurate Behavioral Simulation of Digital Designs
IEEE Transactions on Computers
Reducing Null Messages in Misra's Distributed Discrete Event Simulation Method
IEEE Transactions on Software Engineering
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimistic parallel simulation of continuous time Markov chains using uniformization
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
The effect of memory capacity on Time Warp performance
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Efficient algorithms for distributed snapshots and global virtual time approximation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
A new process to processor assignment criterion for reducing rollbacks in optimistic simulation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Parallel timing simulation on a distributed memory multiprocessor
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Distributed deadlock detection
ACM Transactions on Computer Systems (TOCS)
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Exclusive simulation of activity in digital networks
Communications of the ACM
Ultimate: A hardware logic simulation engine
DAC '84 Proceedings of the 21st Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
ADLIB user''s manual
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Information Systems Frontiers
Triggering Creativity in Science and Engineering: Reflection as a Catalyst
Journal of Intelligent and Robotic Systems
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Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor. The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free. Additionally, it includes a new technique [6] for modeling the timing of digital systems that guarantees the accuracy of the simulation results. In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB [2] or VHDL [1]. Behavior models are popular because of their flexibility; however, they execute excruciatingly slow on uniprocessor computers. The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors. In this approach, a design is first partitioned by the user and the behavior models corresponding to the digital components of each partition are assigned to a unique processor of the parallel processor system. In course of execution, a behavior model receives signal transitions from other models through the explicit communication links, termed protocols, that model the connectivity of the digital design. Every model is completely unaware of the existence of other entities in the simulation system and is solely responsible for accurately scheduling its execution on the underlying processor. Thus, scheduling is distributed in the models and the approach, like the Chandy驴Misra algorithm [11], does not require any knowledge of the global simulation time. However, this paper differs from [11] in that 1) it redefines the notion of deadlock in nonfeedback systems [11] as starvation and proposes a new methodology to address it, and 2) introduces a new mode驴驴exception-mode驴, of execution to prevent the occurrence of deadlock in feedback systems. This paper also reports on an implementation of the approach on the 64 node Bell Labs hypercube [3], [4] and the ARMSTRONG [24] system at Brown University. Performance statistics based on the simulation of several representative designs indicate that the approach achieves significant speedup for realistic combinational behavior-level digital systems while the speedup for sequential designs is a function of the system and other factors.Index Terms驴Distributed simulation, digital systems simulation, asynchronous algorithms, parallel processors.