PASCAL language reference manual
PASCAL language reference manual
Logical Design of Digital Systems
Logical Design of Digital Systems
ADLIB user''s manual
IEEE Transactions on Parallel and Distributed Systems
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
VHDL extensions for complex transmission line simulation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Exploiting temporal independence in distributed preemptive circuit simulation
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Simulation and verification II: from timed automata to DEVS models
Proceedings of the 35th conference on Winter simulation: driving innovation
Simulation semantics for min-max DEVS models
AIS'04 Proceedings of the 13th international conference on AI, Simulation, and Planning in High Autonomy Systems
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The authors examine the limitations of the timing semantics in the conventional behavioral simulators and present a preemptive scheduling mechanism for accurate behavioral simulation results. They consider two signal transitions at the input ports of a component, where the second input transition arrives later than the first transition. The first and second input transitions cause first output signal transitions O/sub 1/ and O/sub 2/, respectively, to be generated at the output port of the component. When the logical values of O/sub 1/ and O/sub 2/ conflict with each other and O/sub 1/ arrives later than O/sub 2/, O/sub 1/ is preempted by O/sub 2/. In addition, an input signal to a component whose pulse duration is smaller than the inertial delay of the component, T/sub mip/, is discarded during simulation. Empirical measures for T/sub mip/ relative to the high-to-low and low-to-high propagation delays of the component for TL (transistor-transistor logic), NMOS, and CMOS technologies are presented. This approach has been implemented in the ADLIB-SABLE simulator at Stanford University.