ACM Transactions on Programming Languages and Systems (TOPLAS)
Digital logic testing and simulation
Digital logic testing and simulation
Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
IEEE Spectrum
VHDL links design, test, and maintenance
IEEE Spectrum
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A Preemptive Scheduling Mechanism for Accurate Behavioral Simulation of Digital Designs
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Reducing Null Messages in Misra's Distributed Discrete Event Simulation Method
IEEE Transactions on Software Engineering
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Optimistic parallel simulation of continuous time Markov chains using uniformization
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
The effect of memory capacity on Time Warp performance
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
Efficient algorithms for distributed snapshots and global virtual time approximation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
A new process to processor assignment criterion for reducing rollbacks in optimistic simulation
Journal of Parallel and Distributed Computing - Special issue on parallel and discrete event simulation
IEEE Transactions on Parallel and Distributed Systems
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Parallel timing simulation on a distributed memory multiprocessor
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Distributed deadlock detection
ACM Transactions on Computer Systems (TOCS)
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
GDEVS: A generalized discrete event specification for accurate modeling of dynamic systems
Transactions of the Society for Computer Simulation International
Hardware Description Languages: Concepts and Principles
Hardware Description Languages: Concepts and Principles
Concurrent and Comparative Discrete Event Simulation
Concurrent and Comparative Discrete Event Simulation
Behavioral-Level Fault Simulation
IEEE Design & Test
Designing a Custom DSP Circuit Using VHDL
IEEE Micro
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
On the nature and inadequacies of transport timing delay constructs in VHDL descriptions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generalized discrete event simulation of dynamic systems
Transactions of the Society for Computer Simulation International - Recent advances in DEVS methodology--part II
Large-Scale systems design: a revolutionary new approach in software hardware co-design
AIS'04 Proceedings of the 13th international conference on AI, Simulation, and Planning in High Autonomy Systems
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The DoD's Very high speed integrated circuit Hardware Description Language, VHDL, is aimed at allowing hardware designers to accurately describe, simulate, and validate combinational and sequential hardware designs on computers prior to building a prototype. Since its conception in the early 1980s, an important goal of VHDL has been to execute complex models concurrently and efficiently on parallel processors. To achieve this objective while exploiting the maximum theoretical parallelism, one requires a deadlock-free, asynchronous, distributed, discrete event simulation algorithm. The YADDES approach, proposed in the literature, achieves deadlock-free, distributed, discrete event simulation, but suffers from an important limitation. YADDES assumes that every entity is characterized by a single propagation delay. In contrast, for hardware entities such as gates, flip-flops, ALUs, and microprocessors, two or more propagation delay values are used corresponding to every path between the input and output. While the use of multiple delays aims at accurate representation of reality, often inconsistent events may be generated that must be detected and preempted. This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, $P^{2}EDAS$. $P^{2}EDAS$ represents a significant advancement in that it permits the use of any number of propagation delays for every path between the input and output of every hardware entity. $P^{2}EDAS$ permits, for the first time, accurate, concurrent, asynchronous, and efficient, i.e., deadlock-free and null-message-free, execution of VHDL models of sequential and combinatorial digital designs on parallel processors. A model refers to a VHDL entity. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, it accurately detects and preempts inconsistent events. To achieve efficiency in the simulation of actual system designs, especially large-scale designs, $P^{2}EDAS$ is designed to exploit coarse-grain parallelism, focusing on entities with significant computational complexities. $P^{2}EDAS$ is not limited to VHDL models only, it extends to hardware descriptions described in any high-level hardware description language. This paper presents a detailed description of the algorithm, illustrative examples, and mathematical proofs of correctness, freedom from deadlock, and termination of simulation in finite time. $P^{2}EDAS$ is implemented for VHDL on both a multithreaded shared memory multiprocessor and a network of Pentium-based Linux workstations, configured as a loosely coupled parallel processor. Performance analysis reveals that $P^{2}EDAS$ achieves superior speedup for a number of representative digital designs, including a large computer system驴the DLX architecture.