Exploiting temporal independence in distributed preemptive circuit simulation

  • Authors:
  • P. Walker;S. Ghosh

  • Affiliations:
  • Division of Engineering, Brown University, Providence , RI;Computer Science Dept, Arizona State University, Tempe, AZ

  • Venue:
  • EDTC '97 Proceedings of the 1997 European conference on Design and Test
  • Year:
  • 1997

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Abstract

In digital circuit simulation hidden opportunities for concurrent execution of models often exist, arising from the propagation delay associated with the generation of output events by the circuit models. An event prediction algorithm is developed to identify such parallelism, increasing the simulation execution rate. The algorithm uses an event prediction network and simulates circuits asynchronously and deadlock free, while honoring the preemptive semantics associated with digital circuit simulation.