Symbolic manipulation of Boolean functions using a graphical representation
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
The complexity of design automation problems
DAC '80 Proceedings of the 17th Design Automation Conference
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
The Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
Software support for the Yorktown Simulation Engine
DAC '82 Proceedings of the 19th Design Automation Conference
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The development of high speed, large capacity hardware systems for logic simulation makes Boolean comparison of logic networks feasible for designs of practical importance. Boolean comparison provides a complete check of functional equivalence of two logic networks and is a valuable tool in design verification. This paper describes virtual logic that controls the Boolean comparison process and provides large reductions in the required number of test cases for many practical design problems. The virtual logic is simulated by the logic simulation system at the same time as the two models are simulated for test cases. The virtual logic has the task of generating new test cases such that the entire input space is covered but minimizing the number of test vectors required. Multivalued logic simulation and other techniques are used to achieve the reductions. Since the entire Boolean comparison task is completed without assistance of a general purpose host system the usual communication overhead is avoided.The techniques described are suitable for high speed logic simulators. The simulation system for the work described here was the Engineering Verification Engine (EVE) developed by IBM but other simulation systems provide similar capability.