Multiple-Way Network Partitioning
IEEE Transactions on Computers
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
A data-driven multiprocessor for switch-level simulation of vlsi circuits
A data-driven multiprocessor for switch-level simulation of vlsi circuits
The on-chip parallelism of vlsi circuits
The on-chip parallelism of vlsi circuits
Parallel mixed-level simulation of digital circuits using virtual time
Parallel mixed-level simulation of digital circuits using virtual time
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Predicting the future: resource requirements and predictive optimism
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Concurrency preserving partitioning (CPP) for parallel logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Demand-driven logic simulation using a network of loosely coupled processors
Journal of Systems Architecture: the EUROMICRO Journal
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
Bipartitioning for Hybrid FPGA-Software Simulatio
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
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One of the significant difficulties in partitioning logic circuits for distributed simulation is the lack of a priori knowledge concerning the evaluation frequency of individual circuit elements. A number of researchers have resorted to pre-simulation to estimate these evaluation frequencies. In this paper we empirically investigate the wisdom of relying on pre-simulation results, and evaluate the degree to which early evaluation frequencies predict later evaluation frequencies. The results show that, for simulations that use random input vectors, pre-simulation has clear merit in predicting circuit element evaluation frequency. This supports the use of pre-simulation as an input to circuit partitioning algorithms.