ACM Transactions on Programming Languages and Systems (TOPLAS)
High performance parallel logic simulations on a network of workstations
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
Evaluating the use of pre-simulation in VLSI circuit partitioning
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
A static partitioning and mapping algorithm for conservative parallel simulations
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Parallel discrete event simulation on shared-memory multiprocessors
ANSS '91 Proceedings of the 24th annual symposium on Simulation
Scheduling DAG's for Asynchronous Multiprocessor Execution
IEEE Transactions on Parallel and Distributed Systems
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel mixed-level simulation of digital circuits using virtual time
Parallel mixed-level simulation of digital circuits using virtual time
Partitioning WCN models for parallel simulation of radio resource management
Wireless Networks - Special issue: Design and modeling in mobile and wireless systsems
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
DSIM: scaling time warp to 1,033 processors
WSC '05 Proceedings of the 37th conference on Winter simulation
A Design-Driven Partitioning Algorithm for Distributed Verilog Simulation
Proceedings of the 21st International Workshop on Principles of Advanced and Distributed Simulation
A parallel logic simulation framework: study, implementation, and performance
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
| Hi-index | 0.00 |
Based on a linear ordering of vertices in a directed graph, a linear-time partitioning algorithm for parallel logic simulation is presented. Unlike most other partitioning algorithms, the proposed algorithm preserves circuit concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the concurrency preserving partitioning (CPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases, and three conflicting goals can be separately considered in each phase so to reduce computational complexity. A parallel gate-level circuit simulator is implemented on an Intel Paragon machine to evaluate the performance of the CPP algorithm. The results are compared with two other partitioning algorithms to show that reasonable speedup may be achieved with the algorithm.