Automatic partitioner for behavior level distributed logic simulation

  • Authors:

  • Kai-Hui Chang;Jeh-Yen Kang;Han-Wei Wang;Wei-Ting Tu;Yi-Jong Yeh;Sy-Yen Kuo

  • Affiliations:

  • Avery Design Systems, Inc., Andover, MA;Avery Design Systems, Inc., Andover, MA;Graduate Institute of Electronics Engineering, National Taiwan University 1, Taipei, Taiwan, ROC;Graduate Institute of Electronics Engineering, National Taiwan University 1, Taipei, Taiwan, ROC;Avery Design Systems, Inc., Andover, MA;Graduate Institute of Electronics Engineering, National Taiwan University 1, Taipei, Taiwan, ROC

  • Venue:
  • FORTE'05 Proceedings of the 25th IFIP WG 6.1 international conference on Formal Techniques for Networked and Distributed Systems
  • Year:
  • 2005

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Abstract

As the complexity of circuit design increases, verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation is one way to solving the problem. In order to distribute the simulation workload to multiple processors, the design must be carefully partitioned first. While most previous work focus on gate level partitioning, our work extends a previously implemented Verilog gate-level partitioner to support RTL and behavior level partitioning. Techniques to partition special constructs specific to these levels, such as global access, function calls and memory access, are described in this paper. The experimental results show that our techniques are capable of finding partitions which can accelerate simulation.