Efficient Partitioning Method For Distributed Logic Simulation of VLSI Circuits

Authors:
A. Guettaf;P. Bazargan-Sabet
Affiliations:
-;-
Venue:
SS '98 Proceedings of the The 31st Annual Simulation Symposium
Year:
1998

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Abstract

Distributed simulation is expected to provide a significant speed up to simulation run time. Partitioning and load balancing are very in uencing factors for speed up. This paper presents an efficient partitioning method for distributed VLSI circuits simulation. The main features of this method are the use of a logic replication algorithm, a realistic cost function based on precalculated activity of the circuit using a probabilistic algorithm, and a the balance between execution cost and communication cost. A distributed simulator based on a conservative synchronization method has been used to evaluate the performance of the partitioning.