Parallel verilog simulation: architecture and circuit partition

Authors:
Tun Li;Yang guo;SiKun Li;FuJiang Ao;GongJie Li
Affiliations:
National University of Defense Technology, P. R. China;National University of Defense Technology, P. R. China;National University of Defense Technology, P. R. China;National University of Defense Technology, P. R. China;National University of Defense Technology, P. R. China
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

Citing 3
Cited 0

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Abstract

This paper presents parallel Verilog simulation architecture bases on optimistic asynchronous parallel simulation algorithm and MPI library, and proposes a novel efficient module-based partition algorithm combined with pre-simulation partition algorithm. With the presented architecture and partition algorithm, parallel Verilog simulation can get promising speedup, as well as distributed workload and communication cost across processors.