ACM Transactions on Programming Languages and Systems (TOPLAS)
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Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Clustered time warp and logic simulation
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
Dynamic load balancing of a multi-cluster simulator on a network of workstations
PADS '95 Proceedings of the ninth workshop on Parallel and distributed simulation
The dynamic load balancing of clustered time warp for logic simulation
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Actor based parallel VHDL simulation using time warp
PADS '96 Proceedings of the tenth workshop on Parallel and distributed simulation
Cramming more components onto integrated circuits
Readings in computer architecture
Parallel and distributed VHDL simulation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Parallel and Distribution Simulation Systems
Parallel and Distribution Simulation Systems
VHDL Coding Styles and Methodologies
VHDL Coding Styles and Methodologies
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
On Rolling Back and Checkpointing in Time Warp
IEEE Transactions on Parallel and Distributed Systems
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
Proceedings of the seventeenth workshop on Parallel and distributed simulation
XTW, a parallel and distributed logic simulator
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Verilog® hdl: a guide to digital design and synthesis, second edition
Verilog® hdl: a guide to digital design and synthesis, second edition
Asynchronous parallel discrete event simulation
IEEE Transactions on Systems, Man, and Cybernetics, Part A: Systems and Humans
On the scalability and dynamic load-balancing of optimistic gate level simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. In this paper, we examine the performance of a parallel Verilog simulator on large, real designs. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. We develop a parser for Verilog files enabling us to simulate in parallel all synthesizable Verilog circuits. We utilize four circuits as our test benches; the LEON Processor, the OpenSparc T2 processor and two Viterbi decoder circuits. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. A dynamic load balancing approach is also developed which uses a combination of centralized and distributed control in order to accommodate its use for large circuits.