Maintaining consistency between systemC and RTL system designs
Proceedings of the 43rd annual Design Automation Conference
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Journal of Signal Processing Systems
| Hi-index | 0.00 |
This paper describes a compiler, which converts from Verilog to C. The output is then compiled to machine native code and tends to execute faster than native mode Verilog simulation because the compiler preserves only the synthesis semantics, not the simulation semantics, of Verilog and performs logic minimization. Busses of up to 32 or 64 bits can be modeled as C integers whereas larger busses are automatically split. We describe the motivation, method and quality of the results.