ACM Transactions on Programming Languages and Systems (TOPLAS)
Parallel algorithms for VLSI computer-aided design
Parallel algorithms for VLSI computer-aided design
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
Benchmarking Parallel Processing Platforms: An Applications Perspective
IEEE Transactions on Parallel and Distributed Systems
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
Parallel mixed-level simulation of digital circuits using virtual time
Parallel mixed-level simulation of digital circuits using virtual time
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As circuits increase in size and complexity, there is an ever demanding requirement to accelerate the processing speed of logic simulation. Parallel processing has been perceived as an obvious candidate to assist in this goal and numerous parallel processing systems have been investigated. Unfortunately, large speedup figures have eluded these approaches. A large communication overhead due to basic passing of values between processors, elaborate measures to avoid or recover from deadlock and load balancing techniques, is the principal barrier to achieving high speedup. This paper presents an Associative memory architecture which is the basis of a machine APPLES(Associative Parallel Processor for Logic Event Simulation), specifically designed for parallel discrete event logic simulation. A scan mechanism replaces inter-process communication. This mechanism is well disposed to parallelisation. The machine has been evaluated theoretically and empirically.