Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A unifying framework for distributed simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Corolla partitioning for distributed logic simulation of VLSI-circuits
PADS '93 Proceedings of the seventh workshop on Parallel and distributed simulation
On area/depth trade-off in LUT-based FPGA technology mapping
DAC '93 Proceedings of the 30th international Design Automation Conference
Parallel logic level simulation of VLSI circuits
WSC '94 Proceedings of the 26th conference on Winter simulation
Acyclic multi-way partitioning of Boolean networks
DAC '94 Proceedings of the 31st annual Design Automation Conference
Transparent implementation of conservative algorithms in parallel simulation languages
WSC '93 Proceedings of the 25th conference on Winter simulation
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
Parallel logic simulation: an evaluation of centralized-time and distributed-time algorithms
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This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.