Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
Fault Table Computation on GPUs
Journal of Electronic Testing: Theory and Applications
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MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that canefficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problemsolutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly pipelined and parallelarchitecture yields a performance comparable to that of existing special-purpose hardware simulators. MARS has the added advantageof flexibility because its VLSI processors are custom-designed to be microprogrammable and reconfigurable. When programmedas a logic simulator, MARS should be able to achieve 1 million gate evaluations per second.