Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
A highly configurable cache architecture for embedded systems
Proceedings of the 30th annual international symposium on Computer architecture
An adaptive cryptographic engine for internet protocol security architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-Power High-Performance Reconfigurable Computing Cache Architectures
IEEE Transactions on Computers
A highly configurable cache for low energy embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Implications of Executing Compression and Encryption Applications on General Purpose Processors
IEEE Transactions on Computers
A cache design for high performance embedded systems
Journal of Embedded Computing - Cache exploitation in embedded systems
Low power data processing system with self-reconfigurable architecture
Journal of Systems Architecture: the EUROMICRO Journal
Exploring the potential of architecture-level power optimizations
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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A considerable portion of a microprocessor chip is dedicated to cache memory. However, not all applications need all the cache storage all the time, especially the computing bandwidth-limited applications. In addition, some applications have large embedded computations with a regular structure. Such applications may be able to use additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. Thus, we propose adaptive balanced computing (ABC)-dynamic resource configuration on demand from application-between memory and computing resources. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations: finite impulse response and discrete/inverse discrete cosine transform. In order to convert a cache memory to a function unit, we include additional logic to embed multibit output lookup tables into the cache structure. The experimental results show that the reconfigurable module improves the execution time of applications with a large number of data elements by a factor as high as 50 and 60.