Dynamic reconfiguration of FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A Reconfigurable multifunction computing cache architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A reconfigurable coprocessor for a PCI-based real time computer vision system
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
RENCO: A Reconfigurable Network Computer
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Combining Serialization and Reconfiguration for Convolver Designs
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A dynamic instruction set computer
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Guest Editors' Introduction: Advances in Configurable Computing
IEEE Design & Test
Profiling soft-core processor applications for hardware/software partitioning
Journal of Systems Architecture: the EUROMICRO Journal
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In this paper, a low power data processing system with a self-reconfigurable architecture and USB interface is presented. A single FPGA performs all processing and controls the multiple configurations without any additional elements, such as microprocessor, host computer or additional FPGAs. This architecture allows high performance with very low power consumption, a comprehensive alternative to microprocessor or DSP systems. In addition, a hierarchical reconfiguration system is used to support a large number of different processing tasks without the power consumption penalty of a big local configuration memory. Due to its simplicity and low power, this data processing system is especially suitable for portable applications, reducing the disadvantage of FPGAs against ASICS in low power consumption applications [A. Amara, F. Amiel, T. Ea, FPGA vs. ASIC for low power applications, Microelectronics Journal 37 (8) (2006) 669-677].